// Cell names have been changed in this file by netl_namemap on Mon Jan  3 04:00:10 UTC 2022
////////////////////////////////////////////////////////////////////////////// 
//
//  jtag_shdw_reg.v
//
//  General-purpose register that can be read or written via JTAG TAP
//  controller.  This contains a shadow register so that the q output will
//  always be the 'official' jtag version
//
//  Original Author: Chris Jones
//  Current Owner:   Behram Minwalla
//
////////////////////////////////////////////////////////////////////////////// 
//
// Copyright (C) 2011 Synopsys, Inc.  All rights reserved.
//
// SYNOPSYS CONFIDENTIAL - This is an unpublished, proprietary work of
// Synopsys, Inc., and is fully protected under copyright and trade secret
// laws.  You may not view, use, disclose, copy, or distribute this file or
// any information contained herein except pursuant to a valid written
// license agreement. It may not be used, reproduced, or disclosed to others
// except in accordance with the terms and conditions of that agreement.
//
////////////////////////////////////////////////////////////////////////////// 
//
//    Perforce Information
//    $Author: ameer $
//    $File: //dwh/up16/main/dev/pcs_raw/dig/rtl/jtag_shdw_reg.v $
//    $DateTime: 2013/12/17 07:13:28 $
//    $Revision: #3 $
//
////////////////////////////////////////////////////////////////////////////// 

`timescale 1ns/10fs
module dwc_e12mp_phy_x4_ns_jtag_shdw_reg #(parameter WIDTH=2,
                       parameter [WIDTH-1:0] RST_VAL = 0,
                       parameter [WIDTH-1:0] SHDW_EN = {WIDTH{1'b1}} // SHDW Register is enabled by default.
                       ) (
output wire [WIDTH-1:0] q,
output wire             serial_out,
input  wire             rst,
input  wire             clk,
input  wire             clk_n,
input  wire             capture,
input  wire             update,
input  wire             shift,
input  wire             select,
input  wire [WIDTH-1:0] capture_val,
input  wire             serial_in
);
    
// Shadow register captures parallel capture_val data when
// clocked but not shifting.  When shifting, LSB is shifted
// onto serial_out and MSB is set via serial_in.
//
reg [WIDTH-1:0] shadow;

assign 		serial_out = shadow[0];

// Need to special-case the single-bit case since the shift operation has to look
// different for that case.
// 
generate
  if (WIDTH == 1) begin: single_bit_gen
    always @(posedge clk or posedge rst)
      if (rst)
        shadow <= 1'b0;
      else if (select) begin
        if (shift)
          shadow <= serial_in;
        else if (capture)
          shadow <= capture_val;
      end
  end 
  else begin: multi_bit_gen
    always @(posedge clk or posedge rst)
      if (rst)
        shadow <= {WIDTH{1'b0}};
      else if (select) begin
        if (shift)
          shadow <= {serial_in, shadow[WIDTH-1:1]};
        else if (capture)
          shadow <= capture_val;
      end
  end
endgenerate

// Output register is reset asynchronously and set synchronously
// from the shadow shift register whenever the update clock rises.
//

// Based on Parameter values insert negedge flop or not on q output.
reg [WIDTH-1:0]   q_reg;

genvar 		  shdw_i;
generate
  for (shdw_i = 0; shdw_i < WIDTH; shdw_i = shdw_i + 1)
    begin: SHDW_LOOP
      
      if (SHDW_EN[shdw_i]) begin: shdw_flop_gen
        
        // Update Q on falling edge during Update.
        always @(posedge clk_n or posedge rst)
          if (rst)
            q_reg[shdw_i] <= RST_VAL[shdw_i];
          else if (select & update)
            q_reg[shdw_i] <= shadow[shdw_i];

        assign q[shdw_i] = q_reg[shdw_i];

      end 
      else begin: shdw_dummy_gen

        // Insert a dummy flop (to be optimized out later) to remove X's and warnings.
        always @(posedge clk_n or posedge rst)
          if (rst)
            q_reg[shdw_i] <= RST_VAL[shdw_i];
          else if (select & update)
            q_reg[shdw_i] <= RST_VAL[shdw_i];

          // Pass shadow value straight out to endpoint.
          assign q[shdw_i] = shadow[shdw_i];
      end

    end // block: SHDW_LOOP
endgenerate
   
endmodule
